The present invention relates to a select signal generating circuit in a semiconductor integrated circuit. More particularly, it relates to a select signal generating circuit, such as a shift register generating select signals for selecting one of plural bus lines or a pipeline processing circuit generating select signals for selecting a word line in a semiconductor memory device, in accordance with a clock signal.
FIG. 1 is a schematic circuit diagram of a first shift register 100 of the prior art. The shift register 100 generates select output signals Q0 to Q3 for selecting one of signal lines, such as bus lines, in accordance with complementary clock signals CK and XCK. FIG. 2 is a timing chart illustrating the operation of the shift register 100.
The shift register 100 includes a plurality of flip-flops each of which includes a master stage for generating a master output signal and a slave stage for generating a slave output signal. The shift register 100 is provided with a reset signal XR.
At the time power is provided to the shift register 100, master output signals MQ0 to MQ3, slave output signals SQ0 to SQ3 and the select output signals Q0-Q3 are unsettled.
In order to initialize the select output signals Q0-Q3, when the reset signal XR falls, the clock signal CK falls, and the clock signal XCK rises, the master stage is initialized, and the master output signal MQ3 rises. Subsequently, the clock signal CK rises, and the clock signal XCK falls. The slave stage and the select output signals Q0-Q3 are initialized, and only the select output signal Q3 rises. Thereafter, every time the clock signal CK rises, the select output signals Q0-Q3 rise in order.
The select output signals Q0-Q3 are unsettled until the reset signal XR is provided since power on. Therefore, simultaneous selection of a plurality of signal lines may cause a bus conflict. The bus conflict may cause the through current to flow between circuits that are connected together by the signal lines, thus deteriorating the system.
FIG. 3 is a schematic circuit diagram of a second shift register 120 which can reset the select output signals Q0-Q3 based on a power-ON detection signal G of the prior art. The power-ON detection signal G is generated by a power-ON detection circuit 140 shown in FIG. 4. FIG. 5 is a timing chart describing the operation of the power-on detection circuit 140 upon power on.
The power-ON detection circuit 140 includes inverter circuits 1a to 1g connected in series. A low-potential power supply Vss is connected to the input terminal of the first inverter circuit 1a, and the output signal of the last inverter circuit 1g is provided to a one-shot pulse generating circuit 2.
A capacitor C1 is connected between a node A, which locates between the inverter circuits 1a and 1b, and the low-potential power supply Vss. A capacitor C3 is connected between a node C, which locates between the inverter circuits 1c and 1d, and the low-potential power supply Vss. A capacitor C5 is connected between a node E, which locates between the inverter circuits 1e and 1f, and the low-potential power supply Vss. A capacitor C2 is connected between a node B, which locates between the inverter circuits 1b and 1c, and a high-potential power supply Vcc. A capacitor C4 is connected between a node D, which locates between the inverter circuits 1d and 1e, and a high-potential power supply Vcc.
When the supply voltage Vcc gradually rises as the supply voltages Vcc and Vss are given, with the node A kept at the level of the supply voltage Vss by the capacitor C1, the capacitor C1 is charged by the output signal of the inverter circuit 1a so that the voltage at the node A rises together with the supply voltage Vcc.
When the supply voltages Vcc and Vss are given, the voltage at the node B rises together with the supply voltage Vcc due to the capacitor C2. Thereafter, when the voltage at the node A rises, the output signal of the inverter circuit 1b is inverted so that the voltage at the node B falls toward a low level.
When the output signal of the inverter circuit 1c is inverted by the dropped voltage at the node B with the node C kept at the level of the supply voltage Vss by the capacitor C3, the capacitor C3 is charged so that the voltage at the node C rises toward a high level.
The voltage at the node D rises together with the supply voltage Vcc due to the capacitor C4. Thereafter, when the output signal of the inverter circuit 1d is inverted due to an increase in the voltage at the node C, the voltage at the node D falls toward a low level.
When the output signal of the inverter circuit 1e is inverted by the dropped voltage at the node D with the node E kept at the level of the supply voltage Vss by the capacitor C5, the capacitor C5 is charged so that the voltage at the node E rises toward a high level.
A node F rises to a high level after a predetermined delay time since power-on of the supply voltage Vcc. The predetermined delay time is determined by the time constant set by ON resistances of the inverter circuits 1a-1g and the capacitances C1-C5 and the rising speed of the supply voltage Vcc.
The one-shot pulse generating circuit 2 generates a one-shot pulse signal (the power-ON detection signal G) at a high level for a predetermined time in response to the rising of the node F.
After power on, when the power-ON detection signal G is provided to the shift register 120 prior to the reset signal XR, the master output signals MQ0-MQ3 and the slave output signals SQ0-SQ3 are reset.
As shown in FIG. 6, therefore, when the power-ON detection signal G is provided, only the master output signal MQ3 and the select output signal Q3 rise, and only the slave output signal SQ3 falls.
The timing of providing the power-ON detection signal G is determined by the time constant set by ON resistances of the inverter circuits 1a-1g and the capacitances C1-C5 and the through rate (rising speed) of the supply voltage Vcc. When the through rate of the supply voltage Vcc is larger than the speed expected at the time of designing the circuit, the power-ON detection signal G is provided to the shift register 120 before the supply voltage Vcc reaches a predetermined level. As a result, the reset operation is not carried out normally. This requires a certain restriction on the power-ON operation. If the power-ON operation lies off the certain restriction, the reset operation fails.
The shift register 120 has transfer gates opened and closed in accordance with the power-ON detection signal G, and charge/discharge circuits connected to the input terminals of latch circuits of the master stage and slave stage. This design inevitably increases the circuit area of the shift register 120 and increases the load capacitance to the latch circuits, thus lowering the operational speed of the shift register 120.
FIG. 7 is a schematic circuit diagram of a third shift register 160 which can reset the select output signals Q0-Q3 in accordance with a reset signal XR1 generated based on the power-ON detection signal of the prior art.
The shift register 160 has the same structure as the shift register 100 except that clock signals CK1 and XCK1 and the reset signal XR1 are provided to the shift register 160.
FIG. 8 is a schematic circuit diagram of a reset signal generating circuit 180 generating the clock signals CK1 and XCK1 and the reset signal XR1. The generating circuit 180 is provided with the clock signal CK, the reset signal XR and power-ON detection signals G and H. The power-ON detection signals G and H are generated by a power-ON detection circuit 200 shown in FIG. 9. FIG. 10 is a timing chart illustrating the operation of the power-ON detection circuit 200. The power-ON detection circuit 200 includes first and second one-shot pulse circuits 3a and 3b connected to the node F of the power-ON detection circuit 140 in FIG. 4.
The first one-shot pulse circuit 3a operates in the same way as the one-shot pulse generating circuit 2 of FIG. 4, thereby generating the power-ON detection signal G. The second one-shot pulse circuit 3b generates the one-shot pulse signal H which rises at the same time as the power-ON detection signal G and falls with a delay from the power-ON detection signal G.
When the power-ON detection signal G rises, the generating circuit 180 generates the clock signal CK1 at a low level irrespective of the level of the clock signal CK. When the power-ON detection signal H rises, the generating circuit 180 invalidates the clock signal CK and generates the reset signal XR1 at a high level irrespective of the level of the reset signal XR.
As shown in FIG. 11, first, the master output signals MQ0-MQ3 are reset in accordance with the low-level clock signal CK1, and the reset signal XR1 generated based on the power-ON detection signals G and H. Then, when the clock signal CK1 rises, the slave output signals SQ0-SQ3 and the select output signals (flip-flop output signals) Q0-Q3 are reset.
The shift register 160 performs the reset operation in accordance with the reset signal XR1 based on the power-ON detection signals G and H. This requires a certain restriction on the power-ON operation, as per the second prior art. If the power-ON operation comes off the certain restriction, the reset operation fails.
FIG. 12 is a schematic circuit diagram of a fourth shift register 220 of the prior art, and FIG. 13 is a timing chart illustrating the operation of the shift register 220.
The shift register 220 has master stages including output latch circuits ML0 to ML2 generating master output signals MQ0 to MQ2. The input terminal of a forward inverter circuit of each latch circuit is connected to the power supply Vcc via a capacitor C. The output terminal of the forward inverter circuit is connected to the power supply Vss via the capacitor C. Each forward inverter circuit includes an N channel MOS (NMOS) transistor and a P channel MOS (PMOS) transistor. The PMOS transistor has a smaller load driving capability than the NMOS transistor. Upon power on, therefore, the master output signals MQ0-MQ2 are reset to low levels.
The shift register 220 has another master stage including a latch circuit ML3 generating a master output signal MQ3. The input terminal of a forward inverter circuit of the latch circuit ML3 is connected to the power supply Vss via the capacitor C. The output terminal of the forward inverter circuit is connected to the power supply Vcc via the capacitor C.
The forward inverter circuit of the latch circuit ML3 includes an NMOS transistor and a PMOS transistor. The PMOS transistor has a greater load driving capability than the NMOS transistor. Upon power on, therefore, the master output signal MQ3 is reset to a high level.
The shift register 220 has slave stages including latch circuits SL0 to SL2, which generate slave output signals SQ0 to SQ2. The input terminal of a forward inverter circuit of each slave stage is connected to the power supply Vss via the capacitor C. The output terminal of the forward inverter circuit is connected to the power supply Vcc via the capacitor C. Each forward inverter circuit includes an NMOS transistor and a PMOS transistor. The PMOS transistor has a larger load driving capability than the NMOS transistor. Upon power on, therefore, the slave output signals SQ0-SQ2 are reset to high levels.
The shift register 220 has another slave stage including a latch circuit SL3, which generates a slave output signal SQ3. The input terminal of a forward inverter circuit of the latch circuit SL3 is connected to the power supply Vcc via the capacitor C. The output terminal of the forward inverter circuit is connected to the power supply Vss via the capacitor C. The forward inverter circuit of the latch circuit SL3 includes an NMOS transistor and a PMOS transistor. The PMOS transistor has a smaller load driving capability than the NMOS transistor. Upon power on, therefore, the master output signal SQ3 is reset to a low level.
With the above-described structure, when the shift register 220 is powered on, the shift register 220 executes the reset operation such that only the select output signal Q3 rises to a high level.
Capacitors are connected to the output terminals of the individual latch circuits of the master stages and slave stages of the shift register 220. This increases the circuit area of the shift register 220, and the load capacitance to each latch circuit increases in normal operation mode so that the operational speed of the shift register 220 falls.
FIG. 14 is a schematic circuit diagram of a first pipeline processing circuit 240 of the prior art. The pipeline processing circuit 240 generates select output signals Q0 to Q7 to select one of plural signal lines in accordance with the clock signal CK. The pipeline processing circuit 240 includes a counter 4, three flip-flop circuits 5a, a decoder 6 and eight flip-flop circuits 5b. 
The counter 4 starts counting up counter output signals B0 to B2 every time the clock signal CK rises in response to the low-level reset signal XR. The counter output signals B0-B2 are respectively provided to the flip-flop circuits 5a, which supply latched output signals CO to C2 to the decoder 6.
The decoder 6 decodes the 3-bit latched output signals C0-C2 and provides the 8-bit decoded output signals D0-D7, one of which is at a high level, to the flip-flop circuits 5b. The flip-flop circuits 5b receive the decoded output signals D0-D7 and output the select output signals Q0-Q7 in accordance with the clock signal CK.
As shown in FIG. 15, each flip-flop circuit 5a includes a master stage and a slave stage. Each of the master and slave stages includes a latch circuit. An input signal D is transferred to the master stage and to the slave stage in accordance with the clock signal CK, thus generating the latched output signal Q. Each flip-flop circuit 5b has the same structure as the flip-flop circuit 5a. 
In the pipeline processing circuit 240, as shown in FIG. 16, when the clock signal CK rises to a high level with the low-level reset signal XR provided, the count-up operation of the counter 4 starts. In the count-up operation, every time the clock signal CK rises, the counter 4 outputs the counter output signals B0-B2.
In response to the rising of the clock signal CK, the three flip-flop circuits 5a latch the counter output signals B0-B2 and output the latched output signals C0-C2.
The decoder 6 decodes the latched output signals C0-C2 of the flip-flop circuits 5a and generates the decoded output signals D0-D7. In response to the rising of the clock signal CK, the eight flip-flop circuits 5b latch the decoded output signals D0-D7 and generate the select output signals Q0-Q7.
In the pipeline processing circuit 240, the counter output signals B0-B2, the latched output signals C0-C2, the decoded output signals D0-D7 and the select output signals Q0-Q7 are unsettled until the low-level reset signal XR is provided since power on. Further, the select output signals Q0-Q7 are unsettled until two periods of the clock signal CK pass after the reset signal XR has fallen to the low level. During the period in which the select output signals Q0-Q7 are unsettled, a plurality of signal lines is selected by the select output signals Q0-Q7, which may cause a bus conflict.
FIG. 17 is a schematic circuit diagram of a second pipeline processing circuit 260 of the prior art. The pipeline processing circuit 260 resets the select output signals Q0-Q7 in accordance with the power-ON detection signal G. The counter 4 and flip-flop circuits 7a and 7b are provided with the power-ON detection signal G from the power-ON detection circuit 140 of FIG. 4.
The counter 4 resets all of the counter output signals B0-B2 to zero (0) in response to the power-ON detection signal G.
In each flip-flop circuit 7a, as shown in FIG. 18, the latched output signal MQ0 of the master stage and the latched output signal SQ0 of the slave stage are both reset to high levels by the high-level power-ON detection signal G. Each flip-flop circuit 7b operates in the same way as the flip-flop circuit 7a. Therefore, the latched output signals C0-C2 of the flip-flop circuits 7a and the select output signals Q0-Q7 of the flip-flop circuits 7b are reset to low levels in accordance with the power-ON detection signal G.
In the pipeline processing circuit 260, as shown in FIG. 19, the counter output signals B0-B2 are all reset to zero in accordance with the power-ON detection signal G, thus resetting all of the latched output signals C0-C2 of the flip-flop circuits 7a to zero. The latched output signals C0-C2 reset all of the decoded output signals D0-D7 to zero, thus resetting all of the select output signals Q0-Q7 to zero.
Because the select output signals Q0-Q7 are all reset to zero after the power-ON detection signal G is provided, a bus conflict by multiple selection of signal lines is prevented.
Although the power-ON detection signal G is used in the pipeline processing circuit 260, a certain restriction is needed on the power-ON operation so that when the power-ON operation goes off the certain restriction, a failure occurs in the reset operation. Further, the number of components of the flip-flop circuits 7a and 7b increases, thereby increasing the circuit area of the pipeline processing circuit 260.
Accordingly, it is an object of the present invention to provide a select signal generating circuit that prevents a malfunction and an increase in the circuit area.
In one aspect of the present invention, a select signal generating circuit includes a select signal generator for generating a plurality of select output signals in accordance with a clock signal in response to a reset signal provided after a predetermined time passes since power on and a power-ON detection circuit for detecting the power-on, generating a power-ON detection signal and maintaining the power-ON detection signal until the reset signal is provided. The select signal generator includes a clamp circuit connected to the power-ON detection circuit for clamping the plurality of select output signals to predetermined levels in response to the power-ON detection signal.
In another aspect of the present invention, a select signal generating circuit includes a select signal generator for generating a plurality of select output signals in accordance with a clock signal in response to a reset signal provided after a predetermined time passes since power on and a power-ON detection circuit for detecting the power-on, generating a first power-ON detection signal at a first level and generating a second power-ON detection signal at a second level in response to the reset signal. The select signal generator includes a clamp circuit connected to the power-ON detection circuit for clamping the plurality of select output signals to predetermined levels in response to the first power-ON detection signal and unclamping the plurality of select output signals in response to the second power-ON detection signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.